ARM架构下Turbo译码时延性能研究
DOI:
CSTR:
作者:
作者单位:

作者简介:

通讯作者:

中图分类号:

TN911.22

基金项目:


Research on Turbo decoding delay performance under ARM architecture
Author:
Affiliation:

Fund Project:

  • 摘要
  • |
  • 图/表
  • |
  • 访问统计
  • |
  • 参考文献
  • |
  • 相似文献
  • |
  • 引证文献
  • |
  • 资源附件
  • |
  • 文章评论
    摘要:

    为了适应基于5G的物联网技术的快速发展,以ARM架构作为物联网终端设备的构想具有重要的实际应用意义。但ARM架构能否满足5G物联网终端性能要求仍然不明确,特别是终端对于海量数据的处理时延将直接影响其实际可行性。鉴于此,基于开源的空中接口平台(OAI),本文重点研究了采用ARM架构的Turbo译码时延问题,并与x86架构计算机进行对比。测试结果表明,基于ARM架构的译码延时要比基于x86架构的译码延时长20%~25%,鉴于两种架构性能上的差异,这一延时差距符合预期。

    Abstract:

    In order to adapt to the rapid development of IoT technologies based 5G, the idea of using the ARM architecture as a terminal device for IoT has important practical significance. However, it is still unclear whether the ARM architecture can meet the 5G IoT terminal performance requirements. In particular, the processing delay of terminal for massive data will directly affect its feasibility.In view of this, based on the open air interface(OAI), this paper focuses on the Turbo decoding delay problem using the ARM architecture and compares it with the x86 architecture computer.The results show that the decoding delay based on the ARM architecture is 20%~25% longer than that of x86 architecture. Given the difference in the performance of the two architectures, this gap is in line with expectations.

    参考文献
    相似文献
    引证文献
引用本文

潘超,陈阳杰,谭国平,李岳衡. ARM架构下Turbo译码时延性能研究[J].电子测量技术,2019,42(7):113-117

复制
分享
文章指标
  • 点击次数:
  • 下载次数:
  • HTML阅读次数:
  • 引用次数:
历史
  • 收稿日期:
  • 最后修改日期:
  • 录用日期:
  • 在线发布日期: 2021-08-09
  • 出版日期:
文章二维码
×
《电子测量技术》
财务封账不开票通知