This paper introduces a design method of radar data acquisition system, which developed a timing circuit by FPGA based on the Beidou SoC. The circuit generates all timing signals which radar needs when accesses it, and adds Beidou time to radar data. In order to achieve the time precision of data acquisition system required, the timing signals are kept step with 1PPS signal output by Beidou, which ensures the radar ranging system and angle encoder systems correctly placed the data on the data bus. The design realized data collection, track simulation, data forwarding, Karman filtering and other functions, reducing the system interface board, integration and stability is greatly improved. It plays an important role to the miniaturization of the radar data acquisition system.