This paper proposes a faulttolerant design method for SRAMbased FPGA by using dynamic reconfiguration technology. This method adjusts the degree of redundancy of the system depending on the various soft error rate. When the error rate is low, the system adopts duplication with compare (DWC) which has lower area overhead and power consumption. If the soft error rate is high, the system switches to the triple modular redundancy (TMR) to eliminate the effects of a single error. By taking the representative circuits in ISCAS’85 benchmark as redundant modules, this paper explains the implementation of faulttolerant structure of dynamic reconfiguration by using Proxy LUT and EAPR (earlyaccess partial reconfiguration) technology. Finally, the paper compares the simulation results with the stateoftheart static fault tolerant technique and thus validates the advantages of the proposed method in the aspects of area and power consumption, its area overhead and power consumption is small.