基于FPGA的双FLASH数据记录器设计与实现
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中北大学 电子测试技术国家重点实验室 太原 030051

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TN914.3

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山西省“1331工程”重点学科建设计划(1331KSC)资助


Design and implementation of double FLASH data recorder based on FPGA
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National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051,China

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    摘要:

    在导弹、火箭等武器装备的研发试验过程中,需要对试验过程中产生的数据进行采集、存储与事后回读分析,针对传统技术无法对速率差较大的两种数据源的数据同时进行高速数据存储的问题,设计了一种基于FPGA的双FLASH数据记录器。采用两块8GB NAND FLASH并行存储方案同时存储400Mbp速率的千兆以太网数据和10Mbps的PCM数据,FLASH采用Multi-Plane方法进行数据读写,由于FLASH固有特性会使存储数据产生误码,设计汉明码校验码纠错方案对误码进行纠错。试验测试与数据分析结果表明,综合数据写数据速率可达410Mbps,回读数据速率可达310Mbps,数据记录器的读写测试误码率为0,满足武器装备的数据存储测试要求,可稳定保存武器装备在高温、高冲击等恶劣环境下试验过程中产生的数据。

    Abstract:

    In the research and development test process of missiles, rockets and other weapons and equipment, it is necessary to collect, store, and read back and analyze the data generated during the test. For traditional technology, it is impossible to simultaneously perform high-speed data from two data sources with large speed differences. For the problem of data storage, a dual FLASH data logger based on FPGA is designed. Two 8GB NAND FLASH parallel storage solutions are used to store 400Mbp Gigabit Ethernet data and 10Mbps PCM data at the same time. FLASH adopts the Multi-Plane method for data reading and writing. Due to the inherent characteristics of FLASH, the stored data will cause errors. Design Hamming code check code error correction scheme corrects the error code. Test and data analysis results show that the comprehensive data write data rate can reach 410Mbps, the readback data rate can reach 310Mbps, and the data logger's read and write test error rate is 0, which meets the data storage test requirements of weapons and equipment, and can be stored stably Data generated during the test of weapons and equipment in harsh environments such as high temperature and high impact.

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孙晓磊,王红亮,陈 航.基于FPGA的双FLASH数据记录器设计与实现[J].电子测量技术,2021,44(23):36-41

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  • 在线发布日期: 2024-07-02
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