Aiming at the requirements of high precision, low noise, high resolution and programmable pulse signals in the fields of radar, communication, electronic metrology and testing, a picosecond-level adjustable pulse width pulse code generation circuit is designed to generate multi-mode and multi-function serialized pulse code signals with precise and controllable pulse width. The pulse code generation circuit is based on the principle of fractional frequency division. By changing the fractional frequency division ratio, the fractional spurious is moved to the high frequency band and filtered by the loop low-pass filter to reduce the noise of the pulse signal. On this basis, the target signal is generated by the parallel-series conversion chip and the clock signal is provided to the FPGA to make up for the shortcomings of low clock frequency and poor accuracy of the FPGA itself. The test results show that the pulse frequency range generated by the pulse generating circuit is 1mHz~400MHz, Minimum pulse width duty cycle step is %~ The output signal type of the pulse signal generation circuit can select the pulse code type signals in the pulse code format of return-to-zero code, non-return-to-zero code, return-to-zero code and pseudo-random code.