The rapid development of industries such as the Internet of Things, automobile manufacturing, and smart medical care has accelerated the promotion and application of endpointdevice chips, and subsequent chip security issues have also been exposed. Traditional micro control unit（MCU）or ARMA series CPU chips can no longer meet the increasingly complex application requirements.In order to solve the problems of insufficient chip security protection, slow transmission speed, high power consumption, and insufficient computing resources in current end devices, combined with the SoC design concept, this paper proposes a cryptographic SoC design scheme based on highspeed bus.This scheme realizes the acquisition of the dynamic status of the sensors, chips, and hardware of the enddevice, receiving multiple highspeed protocol interface data, encrypted storage, and backup to the cloud.The solution uses an opensource processor to complete a lowpower encryption monitoring chip that combines a processor, a highspeed bus, hardware peripherals, and an encryption unit.Synthesis and power analysis and experimental results show that highspeed and reliable data transmission and encryption are realized to meet the needs of fast encryption and decryption of largecapacity data; low power consumption design is adopted, performance is not affected, and power consumption is reduced by about 20%.