With the increasing resolution of highresolution satellite payload CCD cameras, the amount of image data they obtain has sharply increased. How to transmit payload data to backend devices for processing at high speed and reliability is a problem that must be solved. This article conducts research on the high-speed serial interface chip TLK2711 and the same source clock, and analyzes the transmission errors and other issues that may occur in the high-speed data transmission link of the onboard TLK2711. A high-peed data transmission interface design based on the low complexity CRC algorithm is proposed, and the reliability analysis of high-speed data transmission is carried out from both hardware and logic aspects. In terms of hardware, it is based on the same origin clock, providing reference clocks for FPGA and TLK2711 at the sending and receiving ends. In terms of logic, it uses the FB-SC-CRC verification method to provide technical support for data monitoring and error correction during high-speed transmission, reducing resource consumption during data transmission. Through experimental verification, the data transmission interface has achieved reliable data transmission through the use of homologous clocks, with a bit rate of up to 1 600 Mbit/s and an error rate of 0. The use of logical resources has been reduced by about 2/3 compared to traditional CRC.