With the continuous development of ultra large scale integrated circuits, the design of on-chip power supply networks is becoming increasingly important, and it is necessary to reflect the performance of the design by calculating the static voltage drop of the power supply network. However, traditional computing methods require a significant amount of time, resulting in an extended chip design cycle. In order to shorten the cycle of chip design and improve the efficiency of chip design, this paper proposes a fast static voltage drop prediction model based on Convolutional Neural Network ResCSP-34. The model adopts an encoder decoder structure. Firstly, the residual network ResNet34 is modified as the main structure of the encoder. Then, a feature fusion module CSP (Cross Stage Partial) is introduced into the decoder, and a CBAM (Convolutional Block Attention Module) attention mechanism module is introduced at the connection between the encoder and decoder. Finally, a method combining Mean Square Error (MSE) is proposed, Train the model using loss functions such as Pearson Correlation Coefficient (PCC) and Mean Absolute Error (MAE). The experimental results show that on the CircuitNet dataset, the average MAE of the model"s prediction results is 0.7mv, less than 1mv, and the average Pearson correlation coefficient is greater than 0.93, close to 1. The average total time for static voltage drop prediction of an on-chip power supply network design is 7.36 seconds, and the average inference time of the convolutional neural network is 0.015 seconds. The experimental results show that the ResCSP-34 model can quickly and accurately predict static voltage drop.