With the continuous advancement of artificial intelligence technology, the scale of data in neural networks is gradually expanding, leading to a rapid increase in computational complexity. In order to reduce the computational load of SpatioTemporal Graph Convolutional Neural Networks (ST-GCN), decrease hardware resource consumption, and improve processing speed in practical applications of human skeleton recognition systems, a hardware accelerator based on ST-GCN was designed and developed using Field Programmable Gate Arrays (FPGA). By optimizing the structure of the original network model and quantifying the data, the computational load of FPGA implementation is reduced by about 75%. Based on the sparsity of adjacency matrix, an optimization method for multiplicative and additive operation of sparsity matrix is proposed, which reduces the multiplier resource consumption by about 60%. Experimental validation on human skeleton recognition demonstrated that compared to CPUs, FPGA-accelerated ST-GCN units achieved a speedup of 30.53 at a clock frequency of 100 MHz. The FPGA acceleration for human skeleton recognition achieved a speedup of 6.86.