时空图卷积网络的骨架识别硬件加速器设计
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湖南工业大学轨道交通学院

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TN791

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湖南省学位与研究生教学改革研究项目(2022JGYB183)


Hardware accelerator design for skeleton recognition in spatio-temporal graph convolutional networks
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    摘要:

    随着人工智能技术的不断发展,神经网络的数据规模逐渐扩大,神经网络的计算量也迅速攀升。为了减少时空图卷积神经网络的计算量,降低硬件实现的资源消耗,提升人体骨架识别时空图卷积神经网络(ST-GCN)实际应用系统的处理速度,利用现场可编程门阵列(FPGA),设计开发了一个基于时空图卷积神经网络的骨架识别硬件加速器。通过对原网络模型进行结构优化与数据量化,减少了FPGA实现约75%的计算量;利用邻接矩阵稀疏性的特点,提出了一种稀疏性矩阵乘加运算的优化方法,减少了约60%的乘法器资源消耗。经过对人体骨架识别实验验证,结果表明,在时钟频率100MHz下,相较于CPU,FPGA加速ST-GCN单元,加速比达到30.53;FPGA加速人体骨架识别,加速比达到6.86。

    Abstract:

    With the continuous advancement of artificial intelligence technology, the scale of data in neural networks is gradually expanding, leading to a rapid increase in computational complexity. In order to reduce the computational load of SpatioTemporal Graph Convolutional Neural Networks (ST-GCN), decrease hardware resource consumption, and improve processing speed in practical applications of human skeleton recognition systems, a hardware accelerator based on ST-GCN was designed and developed using Field Programmable Gate Arrays (FPGA). By optimizing the structure of the original network model and quantifying the data, the computational load of FPGA implementation is reduced by about 75%. Based on the sparsity of adjacency matrix, an optimization method for multiplicative and additive operation of sparsity matrix is proposed, which reduces the multiplier resource consumption by about 60%. Experimental validation on human skeleton recognition demonstrated that compared to CPUs, FPGA-accelerated ST-GCN units achieved a speedup of 30.53 at a clock frequency of 100 MHz. The FPGA acceleration for human skeleton recognition achieved a speedup of 6.86.

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  • 收稿日期:2024-04-20
  • 最后修改日期:2024-07-05
  • 录用日期:2024-07-08
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