宽带Farrow架构分数时延滤波器优化设计及实现
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作者单位:

南京信息工程大学电子与信息工程学院 南京 210044

中图分类号:

TN98

基金项目:

国家重点研发计划(2022YFB2902100)、江苏省重点研发计划(BE2023088)项目资助


Optimized design and implementation of fractional delay filter for broadband Farrow architecture
Author:
Affiliation:

School of Electronic and Information Engineering,Nanjing University of Information Science and Technology,Nanjing 210044,China

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    摘要:

    可变分数时延滤波器因其能够实现任意分数时延变换而广泛应用于时延补偿技术领域。然而,由于其滤波系数求解复杂度高,适应性差,在工程中应用严重受限。针对这一挑战,本文提出了一种低计算复杂度条件下,通过调节滤波器参数灵活改变分数时延滤波器性能的方法,并完成了FPGA仿真验证。该方法通过调整窗函数的宽度因子来精确控制窗形状,进而优化不同阶数下滤波器的时频特性,提供了比传统方法更精确的频率选择能力。此外,本文采用正交三角分解最小二乘矩阵方法求解滤波器系数,所设计的滤波器在保证群延时精度的条件下,仅需要一次矩阵求逆,有效避免了偏导数和二重积分等复杂数学运算。仿真结果表明,本文提出的方法在保持同等延迟精度条件下,与现有方法相比,计算复杂度降低了一个数量级,最大幅度误差达到-104 dB,最大群延时误差达到2.34×10-4。FPGA验证结果表明,该设计方法硬件计算资源消耗低,极大提高了Farrow滤波器的设计效率。

    Abstract:

    Variable fractional delay filters are widely used in delay compensation technologies due to their ability to achieve arbitrary fractional delay transformations. However, due to the high complexity of solving its filter coefficients and poor adaptability, its application in engineering is severely limited. To address this challenge, this paper proposes a method to flexibly change the performance of fractional time-delay filters by adjusting the filter parameters under the condition of low computational complexity, and completes the FPGA simulation verification. The method precisely controls the window shape by adjusting the width factor of the window function, thereby optimizing the time-frequency characteristics of the filter at different orders and providing more accurate frequency selectivity compared to traditional methods. In addition, this paper adopts the orthogonal triangular decomposition least squares matrix method to solve the filter coefficients, and the designed filter requires only one matrix inverse under the condition of guaranteeing the accuracy of group delay, which effectively avoids the complex mathematical operations such as partial derivatives and double integration. Simulation results show that the method proposed in this paper reduces the computational complexity by one order of magnitude compared with the existing methods under the condition of maintaining the same delay accuracy, with the maximum magnitude error reaching -104 dB and the maximum group delay error reaching 2.34×10-4. FPGA verification results show that the design method has low hardware computational resource consumption, greatly improving the efficiency of the design of the Farrow filter.

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叶霞美,李鹏,冯姣,张治中,郭晓旭.宽带Farrow架构分数时延滤波器优化设计及实现[J].电子测量技术,2025,48(3):1-9

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  • 在线发布日期: 2025-03-20
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