This paper proposes a state acceleration architecture based on programmable hardware, which is built on programmable hardware to realize state management of data plane, so as to realize unified processing of state VNF data transmitted to independent hardware accelerators. Performance analysis results: when more VNF is processed in parallel, it helps to improve the throughput of the SFPA architecture. When four VNF are accelerated in parallel, the hardware acceleration platform will run at full load. After using the resource allocation optimization algorithm, the total amount of SliCE resource consumption in SFPA is reduced. For different VNF, the optimization rate obtained by using this algorithm is also significantly different. When two VNF are accelerated in parallel, the maximum optimization rate obtained is equal to 42%.