Traditionally digital watermarking algorithm is implemented by software method. This paper proposes a high robustness digital watermarking algorithm and an implementation based on FPGA. In this paper, the watermark embedding algorithm is mainly realized by LWT, CS and SVD, where lifting wavelet transform is to decompose the host image to 3 stages and chaotic scrambling algorithm is to encrypt the watermark image and then decompose the LL part of third LWT order using SVD to get the corresponding singular value matrix and last embed the encrypted watermark into the singular value matrix. In the FPGA implementation of this algorithm, the hardware implementation of lifting wavelet transform, chaotic scrambling encryption and matrix SVD decomposition are studied. The experimental results show that the proposed algorithm in this paper is robust, and the watermarked image has strong anti attack ability. The algorithm can be efficiently implemented on FPGA. Finally, the experimental results have been verified, using FPGA to achieve the digital watermarking algorithm is stable and reliable, the watermark embedding rate is greatly improved.