This paper presents an off-chip interleave calibration scheme for the Offset error, Gain error and Skew error of the high sampling rate time-interleaved analog-to-digital converter (TIADC). A time-interleave calibration algorithm is based on statistical approximation. Through Ethernet communication, the quantization information of the channel to be calibrated is transmitted to the PC to extract the mismatch parameters, and the error is compensated in the form of negative feedback. The scheme is not affected by high speed data transmission and synchronization, does not consume logical resources in error extraction stage, supports various large-scale and high-consumption calibration algorithms, and has a short development cycle. When applied to the self-developed 3GS/s -12bit four-way interleaving TIADC, the test results show that the ADC effective bit (ENOB) is increased by 2.69 bits on average in the 2.5G input signal bandwidth under the condition of other non-ideal factors. The calibrated SFDR improved by an average of 29.73 dBc. It is proved that the algorithm and the calibration scheme are effective.