A new parallel cyclic redundant check (CRC) encoding method is proposed in this paper after the introduction of CRC implementation theory and realization method. Serial implementation method takes less resources, but the efficiency is low;While parallel implementation method can complete several bits of CRC calculation at the same time , but takes too much hardware resources. In order to improve the CRC calculation efficiency and reduce resource consumption, this paper proposes a parallel CRC encoding method and then take CRC16 for example, use the Arria V GX series FPGA chip 5AGXFB3H4F35C4N produced by Altera corporation to realize the universal asynchronous receiver/transmitter (UART) communication containing the proposed new CRC encoding method. Finally, call the simulation tool ActiveHDL, the result shows that this method consumes less hardware resources and has the ability to complete the parallel CRC computing at the next clock after the input changed.