Parameterized method for fault test of embedded multiplier

Home > Archive>Volume 39, Issue 6, 2016 >98-101

Parameterized method for fault test of embedded multiplier
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                        Xiao JingXiao Jing
1. Hunan Provincial Key Laboratory Agriculture Intelligent Control Technology, Huaihua 418000, China; 2. Huaihua University, Huaihua 418000, China
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Yang HuipingYang Huiping
1. Hunan Provincial Key Laboratory Agriculture Intelligent Control Technology, Huaihua 418000, China; 2. Huaihua University, Huaihua 418000, China
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He DajiangHe Dajiang
1. Hunan Provincial Key Laboratory Agriculture Intelligent Control Technology, Huaihua 418000, China; 2. Huaihua University, Huaihua 418000, China
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Affiliation:1. Hunan Provincial Key Laboratory Agriculture Intelligent Control Technology, Huaihua 418000, China; 2. Huaihua University, Huaihua 418000, China
Clc Number:TN710
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Abstract:

This paper describes a fault detection and diagnosis method with BIST technology to verify the integrity of the embedded multiplier cores in Alteral’s FPGAs. This approach uses an architecture independent test algorithm implemented by the hardware description language. Through three configuration download, it can detect all kinds of faults in multipliers at the modes of operation. At the same time, it can identify the location of faulty multiplies. Finally, verifying the effectiveness and accuracy of the proposed method through an integral BIST test circuit which based on the test model of measured multiplier.

Key words:FPGA; VHDL; multiplier; BIST

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Online: July 21,2016
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