The common decoding algorithm for TPC codes (Turbo Product Code) is the Pyndiah-Chase-II algorithm, but the Pyndiah-Chase-II algorithm involves a large number of sorting operations, complex branching structures and storage scheduling in the process of searching for the least reliable input bit positions and shortest Euclidean distance code words making it very unfavorable for integrated circuit hardware implementation. In order to solve these problems, proposing a TPC decoding algorithm based on probabilistic computation, the algorithm includes information input layer, random bit stream generation layer, BCH hard judgment layer, BCH&CRC check layer, and output layer, and the sub-code of TPC code adopts BCH code, program design of decoding algorithm and simulation of decoding performance and decoding delay by MATLAB software. The simulation results show that the decoding algorithm can achieve the same decoding performance as the traditional Pyndiah-Chase-II algorithm, and it only needs two iterations on average to achieve correct decoding, which can effectively reduce the decoding delay. Finally, the FPGA-based hardware design is completed. The BCH hard judgment layer is implemented by the lookup table method, and the logic structure of other layers is simple and all are gate-level operations, so it can significantly reduce the hardware overhead and power consumption, and is easy to implement with integrated circuits.