Design of test table of a telemetry device based on FPGA
DOI:
CSTR:
Author:
Affiliation:

1. School of Instrument and Electronics, North University of China, Taiyuan 030051,China; 2. School of Electrical and Control Engineering, North University of China, Taiyuan 030051,China

Clc Number:

TN914.1

Fund Project:

  • Article
  • |
  • Figures
  • |
  • Metrics
  • |
  • Reference
  • |
  • Related
  • |
  • Cited by
  • |
  • Materials
  • |
  • Comments
    Abstract:

    To address the shortcomings of traditional signal source that can only produce single signal and can not be adjusted, and to meet the testing requirements of a certain type of telemetry device, a design scheme of detection table based on the output controlled by upper computer and adjusted by hand is proposed. This paper discusses the detailed analysis and design of the structure and working pri-nciple of the detection table, as well as a brief introduction of the upper computer. The detection table is centred on FPGA, digital mea-suring board and electric relay with the characteristics of high integration, multiplexing, simple structure and convenient operation. The 13 channels of analog signals are adjusted by the upper computer to achieve 0-30V analog voltage. The 1 channel of -230V~0V analog voltage is obtained by the 220V inverter. The test results show that the digital output of the test table is completely correct, and the out-put error of the analog output is less than 1%, which fully meets the requirements of the test, and has strong anti-interference ability, good reuse and practical value.

    Reference
    Related
    Cited by
Get Citation
Share
Article Metrics
  • Abstract:
  • PDF:
  • HTML:
  • Cited by:
History
  • Received:
  • Revised:
  • Adopted:
  • Online: May 14,2024
  • Published:
Article QR Code