In network communication system, image processing system, and so on, multiple subsystems would access external memory simultaneously. Multi-channel memory controller can solve this problem effectively. With the increasement of data and the improvement of processing unit performance, traditional multi-channel controllers can not meet the requirement of high-speed memory access for system because of low bandwidth utilization. To solve the aforementioned problems, we propose a new kind of DDR4 multi-channel controller on the FPGA in this paper. The controller is defined by simplified user interface and supports ring buffer in network communication, which reduces the use complexity and improves the universality. Multi-channel access conflicts can be solved efficiently by adopting circular priority arbiter. Meanwhile, the bandwidth utilization of the system has been improved. Besides, the rewinding access to the ring buffer is realized by a sharding mechanism. The simulation results are consistent with that on Xilinx KCU116 FPGA. When testing 4096 MB records, the maximum effective bandwidth of the system is 78.3Gbps, and the bandwidth utilization rate reaches 94.0%.