In order to generate high resolution and wide dynamic delay sampling pulses, a coarse + fine two-stage delay framework is introduced. The external 0.1~12 GHz clock signal is divided by the phase-locked loop to generate a synchronous clock of about 100~250 MHz to drive the counter to count. When the counter reaches the preset value, a synchronous carry pulse signal with a frequency of 50 kHz is generated, and the resolution is 10 bit and 10 ps. The coarse delay chip and the fine delay chip with a resolution of 0.1 ps start to work and output sampling pulses with a certain delay amount, and the sampling pulse drives the sampler to precisely sample the synchronous radio frequency signal. The test results show that the resolution and dynamic delay range of the digital programmable precision delay trigger can reach 1ps and 10 ns, respectively.